1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a non-volatile memory and fabricating method thereof.
2. Description of the Related Art
Among various types of non-volatile memory products, electrically erasable programmable read only memory (EEPROM) is a memory device that has been widely used in personal computers and electronic equipment. Data can be stored, read out or erased from the EEPROM many times and stored data are retained even after power supplying the devices is cut off.
Typically, the floating gate and the control gate of an EEPROM cell are fabricated using doped polysilicon. In the conventional technique, a charge-trapping layer is sometimes used to replace polysilicon fabricated floating gate. The material of the charge-trapping layer is silicon nitride, for example. In general, an oxide layer is formed both above and below the silicon nitride charge-trapping layer to form an oxide/nitride/oxide (ONO) composite layer. This type of memory is often referred to as a silicon-oxide-nitride-oxide-silicon (SONOS) memory device.
FIG. 1 is a schematic cross-sectional view of a conventional non-volatile memory developed in recent years. As shown in FIG. 1, the non-volatile memory has a memory cell array 117 including a plurality of memory cells 102 and a plurality of memory cells 116. The memory cells 102 and the memory cells 116 are isolated from one another through insulating spacers 110. Each memory cell 102 includes a bottom dielectric layer 104a, a charge-trapping layer 104b, a top dielectric layer 104c (the bottom dielectric layer 104a, the charge-trapping layer 104b and the top dielectric layer 104c together form a composite layer 104), a gate 106 and a mask layer 108 sequentially formed over the substrate 100. The memory cells 116 are disposed between every pair of adjacent memory cells 102. Each memory cell 116 includes a bottom dielectric layer 112a, a charge-trapping layer 112b, a top dielectric layer 112c (the bottom dielectric layer 112a, the charge-trapping layer 112b and the top dielectric layer 112c together form a composite layer 112) and a gate 114 sequentially formed over the substrate 100. Because there is no gap between various memory cells in the non-volatile memory, overall level of integration of the device can be increased.
However, the gates of the memory cells 102 are typically fabricated from polycide material, for example, formed by a doped polysilicon layer 106a and a silicide layer 106b. Because the gate 114 of the memory cell 116 is formed on a non-planar surface, it is difficult to fill a low resistant conductive material such as tungsten silicide inside it. Therefore, the gate 114 can only be formed using a higher resistant material such as doped polysilicon. Since doped polysilicon has a higher resistance, the operating speed of the device is limited that it is difficult to use the device in a high-speed environment.
Furthermore, there is difference in resistance between the material constituting the gate 106 of the memory cell 102 and that constituting the gate 114 of the memory cell 116. That is, the memory cell 116 has a resistance significantly higher than that of the memory cell 102. As a result, the electrical properties between the two memory cells are different and may lead to a drop in device performance and stability.